One of the original designers of RISC-V boldly predicted this week that the open architecture will outperform rival chip architectures in performance.
“[The] the prediction is two or three years, we will exceed your architectures and the performance available with designs that are in flight right now,” said Krste Asanović, professor of computer science at the University of California, Berkeley, during a speech at the Supercomputing 2022 conference.
But Supercomputing show attendees were skeptical of RISC-V’s readiness for high-performance computing, saying it was far from ready as a consumer alternative to x86 or Arm.
Commercial chip companies have estimated a realistic time frame of nearly five years or even more before RISC-V will make a significant dent in the market.
Nonetheless, there was a lot of momentum behind RISC-V at the show, and attendees agreed that the architecture couldn’t be ignored and would eventually make its way into mainstream HPC.
RISC is an open-chip, license-free architecture. Customers can add their own extensions and customize the chip for a number of applications including artificial intelligence, mobile and industrial applications.
RISC-V is not yet a viable market option for high-performance computing, said SiPearl CEO Philippe Notton. HPCwire.
The chipmaker has developed an Arm-based processor called Rhea, which will go into future exascale systems in Europe. The chip has 29 RISC-V microcontrollers to support the Arm processor.
SiPearl was born with funding from the European Union, which has the long-term goal of developing local processors. The European Processor Initiative, which is also funded by the EU, focuses on developing chips with RISC-V to break away from proprietary x86 and Arm technologies.
SiPearl – which was founded in 2019 – needed to quickly deliver a high-performance processor to European consortia involved in creating exascale supercomputers, and Arm was the only option to develop a custom chip.
RISC-V is still far from commercially ready, Notton said, adding that he was open to designing a chip based on the architecture. Until then, Arm has a more reliable hardware and software ecosystem and set of tools that it can provide to customers.
“It’s hard to say because our own RISC-V chip will have to be serious about HPC,” Notton said.
If RISC-V emerges, Arm will react and do something about it, Notton said.
Intel is working closely with the Barcelona Supercomputing Center to build a RISC-V chip for supercomputing. But RISC-V for HPC is “many years away,” said Jeff McVeigh, vice president and general manager of the Super Compute Group at Intel.
BSC hopes to add a capable RISC-V processor to the European roadmap and has a rich history of experimenting with new chips. The Supercomputing Center’s partnership with Intel is more about incorporating a RISC-V core into chiplets, which is a new type of chip design in which multiple processor modules can be crammed into a single chip package.
The future of Intel’s manufacturing revolves around chips, which will add design flexibility with the ability to put processors, GPUs, I/O, memory types, power management, and other circuits in a chip package. Intel is developing a server chip called Falcon Shores for 2025, which will incorporate Intel’s GPU and x86 CPU design as a chiplet.
The BSC partnership envisions future variants beyond Falcon Shores that allow integration of RISC-V as a primary CPU alternative to x86, McVeigh said.
There’s still a lot of work to do to bring RISC-V to HPC beyond chip design, McVeigh said.
“We’ll see. It’s a long process of porting code, performance, all of those things, but we think there’s a potential future,” McVeigh said.
The most enthusiastic RISC-V backers were university researchers designing indigenous chips for Europe.
The Jülich Supercomputing Center in Germany, home to some of the world’s fastest supercomputers, is interested in many architectures, including RISC-V, said Estela Suarez, head of RG next-generation architectures and prototypes at Forschungszentrum Jülich.
“We’re kind of on the upper layer of software development. We make sure the hardware stack is supported,” Suarez said.
RISC-V is designed as a modular instruction set with a very small base of less than 50 instructions. Custom cores that can be glued to the base ISA like Lego blocks. RISC-V’s expansiveness is seen as a strength over its integration-based rivals.
Weaponization of chips by countries and regions has intensified efforts to create indigenous chips in Europe and China based on RISC-V. The United States has banned the export of advanced processors and GPUs to China. The United States has also banned all semiconductor exports to Russia, where companies like Yadro also have RISC-V designs in the pipeline.
The European Processor Initiative expects native RISC-V accelerators for applications such as AI to be much faster than general-purpose processors.
EPI’s high-performance accelerator called EPAC, based on the RISC-V architecture, features Avispado vector processing units developed by Semidynamics and a RISC-V processor developed by France-based Kalray. It also has a tensor accelerator and an integrated FPGA for reconfigurable logic.
The first EPAC release was registered last month, and a follow-up, EPAC-2 is on the roadmap for 2024. The EPAC-2, with the Rhea 2 chip, is intended for deployment in European exascale supercomputers at from 2024, according to PPE Roadmap.
“What’s really important is that we have European support to build the whole chain of knowledge you need to make good chips. It’s not enough to have someone with a good architectural idea on a blackboard,” said Filippo Mantovani, senior researcher at the Barcelona Supercomputing Center.
The most important point is to develop European expertise and a thriving semiconductor ecosystem in the region, which will benefit the region’s chip companies, said Mantovani, who also leads accelerator development at EPI.
The BSC and other universities also participated in the development of Monte Cimone, a high-performance computer based on the RISC-V architecture.
The Monte Cimone cluster includes eight compute nodes in four blades. Each node has SiFive’s U740 chip, which has four 64-bit U74 cores with frequencies up to 1.2 GHz. The systems – which were SiFive HiFive Unmatched cards – had 16GB of DDR4 memory, 1TB of NVMe storage and PCIe expansion cards, according to a research paper talking about the system.
The system was created to test applications and their performance, much like the Mont Blanc system over a decade ago, which was used to test Arm processors in HPC environments. Arm processors are now in the world’s second fastest supercomputer, called Fugaku, which is deployed at the Riken Center for Computational Science in Japan.
Monte Cimone’s study noted that although RISC-V deployments are growing and the software stack is maturing rapidly, it is still “clear that the performance and number of cores in the SoC are not sufficient to achieve performance comparable to mature Arm and x86 cores. ”
RISC-V International, which manages the development of the ISA, has the support of some of the largest chip manufacturers. ISA is also used in a TPU chip developed by Google, and Intel and SiFive showed off a computer board called Horse Creek, which was made using the Intel 4 process and supports the latest DDR5 memory and PCIe 5.0 interface.
Asanović argued that historical computing trends were in favor of RISC-V. Instruction sets widely used in high-performance computing at times, including DEC’s Alpha, Intel’s Itanium, and Oracle’s SPARC, are gone.
Proprietary chip designs such as x86 and Arm could face challenges as more chips are customized. The x86 architecture dominated the era of “cards” which focused on integration, and Arm dominated the mobile era with modems and integrated GPUs. But as chip customization grows, companies are averse to betting their future on proprietary design, and RISC-V makes more economic sense and can be scaled to more computing capabilities.
RISC-V International has a special interest group for HPC and has ongoing plans to add HPC capabilities to RISC-V. Many people from academia and industry also contribute to the ISA, making it a community effort.
“We even have a basic 128-bit address version in draft form, because we’ll need it by the end of the decade,” Asanović said.
Right now, HPC just isn’t a big enough market to justify custom silicon, so the chip model will help design chips with accelerators at a reasonable cost.
“RISC-V…is inevitable,” Asanović said, adding “think Ethernet. Think Linux. That’s what’s happening with RISC-V.
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