Engineers from Caltech and the University of Southampton in England have collaboratively designed an electronic chip integrated with a photonic chip (which uses light to transfer data) – creating a coherent end product capable of transmitting information at very high speeds while generating minimal heat.
While the two-chip sandwich is unlikely to end up in your laptop, the new design could influence the future of data centers that handle very high volumes of data communication.
“Every time you make a video call, stream a movie, or play an online video game, you’re routing data to a data center for processing,” says Caltech graduate student Arian Hashemi Talkhooncheh, author lead of an article describing the two-chip innovation that was published in the IEEE Journal of Solid State Circuits November 3.
“There are more than 2,700 data centers in the United States and more than 8,000 worldwide, with server towers stacked on top of each other to handle the load of thousands of terabytes of data coming in and going out every second.
Just as your laptop gets hot on your lap while you’re using it, the server towers in data centers that keep us all connected also get hot while they’re running, but on a much larger scale. Some data centers are even built under water to more easily cool the entire facility. The more efficient they are, the less heat they will generate and ultimately the more information they can handle.
Data processing is done on electronic circuits, while data transmission is done more efficiently using photonics. Achieving super-fast speed in each area is very difficult, but designing the interface between them is even more difficult.
“There is a continuous demand to increase the speed of data communication between different chips, not only in data centers, but also in high-performance computers. As the computing power of chips evolves, the communication speed can become a bottleneck, especially under tight energy constraints,” says Azita Emami, Andrew and Peggy Cherng Professor of Electrical and Medical Engineering; Chief Electrical Engineering Officer; and lead author of the article.
To meet this challenge, the Caltech/Southampton team designed both an electronic chip and a photonic chip from scratch and co-optimized them to work together. The process, from initial idea to final lab test, took four years, with each design choice having an impact on both chips.
“We had to optimize the whole system at the same time, which resulted in higher energy efficiency,” says Hashemi. “These two chips are literally made for each other, integrated with each other in three dimensions.”
The resulting optimized interface between the two chips allows them to transmit 100 gigabits of data per second while producing only 2.4 pico-joules per transmitted bit. This improves the electro-optical power efficiency of the transmission by a factor of 3.6 compared to the current state of the art. A picojoule is one trillionth of a Joule, which is defined as the energy released in one second by a current of 1 amp through a 1 ohm resistor, or about 0.24 calories.
“As the world becomes increasingly connected and each device generates more data, it is exciting to show that we can achieve such high data rates while consuming a fraction of the power compared to traditional techniques,” Emma says.
The article is titled “A 100 Gb/s PAM4 Optical Transmitter in a 3D Integrated SiPh-CMOS Platform Using Segmented MOSCAP Modulators”.
Arian Hashemi Talkhooncheh et al, A 100-Gb/s PAM4 Optical Transmitter in a 3-D-Integrated SiPh-CMOS Platform Using Segmented MOSCAP Modulators, IEEE Journal of Solid State Circuits (2022). DOI: 10.1109/JSSC.2022.3210906
Provided by California Institute of Technology
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